The present disclosure relates to capacitor arrays, and layout of a plurality of comb capacitors forming a capacitor array.
Numbers of elements are arranged in a semiconductor integrated circuit, it is thus important how best to utilize limited space on a substrate. In particular, it is important how efficiently to arrange capacitive elements requiring a larger area than other elements. Thus, area-efficient comb capacitors are often used in a semiconductor integrated circuit (see, for example, U.S. Pat. No. 7,022,581).
The capacitance of a comb capacitor depends on the number of comb teeth. Various numbers of comb teeth are employed, thereby forming a capacitor array including a plurality of comb capacitors.
For example, a capacitor array shown in FIG. 7 includes three comb capacitors 100, 110, and 120. The comb capacitors 120, 110, and 100 have 1, 2, and 8 comb tooth/teeth, respectively. The comb teeth of the comb capacitors 100 and 110 are symmetrically arranged relative to the comb tooth of the comb capacitor 120, thereby averaging the tilt of the surfaces of layers of a semiconductor integrated circuit to increase the matching ratio of the comb capacitors (see, for example, U.S. Patent Publication No. 2006/0270145).